The present invention relates, in general, to the field of integrated circuit (IC) memory devices. More particularly, the present invention relates to the field of non-volatile, ferroelectric random access memory (F-RAM) devices and a method for fabricating a damascene self-aligned F-RAM device structure on a planar surface using a reduced number of masks and etching steps.
According to World Semiconductor Trade Statistics (WSTS), the semiconductor market reached an important milestone in 2010, posting worldwide revenues of more than $300 billion (in United States dollars) for the first time in the industry's history. In particular, the memory chip segment exhibited the highest growth rate during 2010, increasing from $45 billion in 2009 to $71 billion in 2010, representing a 57% year-over-year growth rate. Embedded memory devices represented more than 23% of the overall semiconductor market in 2010.
Within this context, the increasing demand for higher processing power is driving the semiconductor industry to develop memory devices with higher operational speeds in order to support the capabilities of modern electronic devices. F-RAM has emerged as a promising option for the industry, particularly in the market areas of mobile computing, smart meters, radio frequency identification (RFID) devices, office equipment and other applications requiring non-volatile data storage.
Standard dynamic random access memory (DRAM) and static random access memory (SRAM) devices, while providing relatively fast access times, are considered to be volatile memory devices inasmuch as data stored in such memories is lost when power is interrupted. In contrast, non-volatile memory devices are those that function to retain data despite any loss of power.
F-RAM devices are inherently non-volatile, meaning that these memory devices are able to retain stored data while the device is not powered. In comparison to electrically erasable programmable read only memory (EEPROM) FLASH memory devices, which are currently the most popular type of non-volatile memory, F-RAM devices have several advantages including lower power requirements (operational voltages of just 5V needed during read-write operations), higher read-write speeds (less than 70 nanoseconds), and virtually unlimited write endurance capability (more than 10,000,000,000 write cycles).
F-RAM memory devices may be fabricated based on the use of lead zirconium titanate (PZT) ferroelectric storage capacitors as memory elements integrated with complementary metal oxide semiconductor (CMOS) addressing, selection, and control logic. PLZT is a lanthanum-doped form of PZT wherein some of the lead is replaced with Lanthanum.
It is also known that PZT may also be doped with strontium and calcium to improve its ferroelectric dielectric properties. Ferroelectric storage capacitors having a strontium bismuth tantalate (SBT); barium strontium titanate (BST); and strontium titanate oxide (STO) dielectrics are also known in the art.
As used in the present application, the term “PZT” shall also be considered to include PLZT, SBT, BST, STO and other comparable ferroelectric dielectric materials. Further, it should be noted that the techniques of the present invention disclosed herein are applicable to all known ferroelectric dielectrics including Perovskites and layered Perovskites (whether doped or undoped) including PZT, PLZT, BST, SBT, STO and others while simultaneously allowing for a potentially broader choice of electrode materials and the use of a forming gas anneal process step on the completed IC structure.
Regardless of the ferroelectric dielectric material employed, in operation F-RAM devices function through their ability to be polarized in one direction or another in order to store a binary value representative of a logic level “one” or “zero”. The ferroelectric effect allows for the retention of a stable polarization state in the absence of an applied electric field due to the alignment of internal dipoles within the Perovskite crystals in the dielectric material. This alignment may be selectively achieved by application of an electric field which exceeds the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles.
A hysteresis curve, wherein the abscissa and ordinate represent the applied voltage (“V”) and resulting polarization (“Q”) states respectively, may be plotted to represent the response of the polarization of a ferroelectric capacitor to the applied voltage. A more complete description of this characteristic hysteresis curve is disclosed, for example, in U.S. Pat. Nos. 4,914,627 and 4,888,733 assigned to Ramtron International Corporation, assignee of the present invention, the disclosures of which are herein specifically incorporated by this reference.
Representative of the current state of the art in F-RAM device fabrication is that disclosed in U.S. Pat. No. 6,150,184 for: “Method of Fabricating Partially or Completely Encapsulated Top Electrode of a Ferroelectric Capacitor,” also assigned to Ramtron International Corporation. Therein described is the structure of a ferroelectric capacitor that includes a bottom electrode, a top electrode, and a ferroelectric layer located between the top and bottom electrodes that extends to completely encapsulate the top electrode, except for a contact hole to allow metallization of the top electrode. The total encapsulation of the top electrode reduces the sensitivity of the ferroelectric capacitor to hydrogen and thus improves electrical switching performance. The encapsulation technique can also be used to improve the performance of ferroelectric integrated circuits and other devices.
Further representative of the state of the art in the fabrication of F-RAM devices is that disclosed in U.S. Pat. No. 6,613,586 for: “Hydrogen Barrier Encapsulation Techniques for the Control of Hydrogen Induced Degradation of Ferroelectric Capacitors in Conjunction with Multilevel Metal Processing for Non-Volatile Integrated Circuit Memory Devices,” also assigned to Ramtron International Corporation. Therein described is a device structure which ameliorates the hydrogen induced degradation of ferroelectric capacitors by completely encapsulating the capacitor within a suitable hydrogen barrier material, such as chemical vapor deposition (“CVD”) or sputtered silicon nitride (Si3N4), thus ensuring process compatibility with industry standard process steps. Although the deposition process for CVD Si3N4 itself contains hydrogen, the deposition time may be kept relatively short thereby allowing the titanium nitride (TiN) local interconnect layer to act as a “short term” hydrogen barrier.
The disclosures of U.S. Pat. Nos. 6,150,184 and 6,613,586 are herein specifically incorporated by this reference in their entirety.
Despite the aforementioned advantages over volatile memory devices and other non-volatile technologies, F-RAMs currently account for a relatively small share of the non-volatile memory device market. Competitively, the main limitation of the F-RAM technology has been its lower storage density compared to FLASH devices coupled with higher manufacturing costs. These limitations stem primarily from the generally complex structure of current F-RAM devices which results in a manufacturing process that requires a high number of processing masks and etching steps. As such, in order to be more competitive in the current memory device marketplace and be usable in a wider range of modern electronic devices, F-RAM devices need to be more highly integrated, implying increased storage densities and reduced manufacturing costs.
As such, it would be highly advantageous to reduce the number of layers and etching steps required during F-RAM fabrication in order to reduce manufacturing costs. Still further, it would be highly advantageous to simplify the structure of F-RAM devices with the purpose of improving storage density capabilities.